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CD2490A 32bit
DSP cores
- Summary of CD2490A -
32 bit Fixed point DSP with strong double word instructions.
Compatible with standard single port clocked memory
IP.
Four sets of double word accumulators.
Strong barrel shifter / normalizer.
Bit stream data handling.
Variable length code handling (e.g. Huffman code).
Table look up capability.
Instruction compatibility with Lower precision DSP (CD2470A,
CD2480A).
No pipeline latency.
6% code space reserved for custom instructions.
Verilog HDL Synthesizable design with visualized block
diagrams.
Communication port with outside Host hardware.
50MIPS for common 90nm Xilinx, Altera FPGA chips.
- Block Diagram of CD2490A -
- Memory I/O Interface with CD2490A -
- Memory I/O Timing of the CD2490A -
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