CD2470A ,80A,90A Summary

1. CD2470A Summary. 3

1.1 CD2470A Block Diagram.. 4

1.2 CD2470A Core Pin Summary. 5

1.3 CD2470A Core – Memory Interface Diagram.. 5

1.4 CD2470A Basic Memory Access Timing Idea. 5

1.5 CD2470A Register summary. 6

1.6 CD2470A Registers Bit assignment. 7

1.7 CD2470A ALU Flag Updating Summary. 9

2. CD2470A 16 Bit DSP Description. 10

2.1 GENERAL DESCRIPTION. 10

Numeric Data Representation and Overflow. 10

Timing. 11

2.2 ALU. 11

2.3 Barrel Shifter / Normalizer. 12

2.4 Multiplier. 12

2.5 Data Registers. 13

Numeric Registers. 13

Status Register 14

Program Counter 15

Other function Registers. 15

2.6 Memories. 17

2.7 Address Pointer Registers. 18

Indirect Addressing. 18

Stacks. 19

2.8 Conditional Instructions. 19

2.9 System Functions. 20

Interrupts. 20

Reset 21

Clock Control 21

3. CD2470A Instruction Details. 23

3.1 CD2470A Instruction summary Table. 23

3.2 CD2470A Instruction condensed code table. 26

4. Appendix. 27

4.1 Cyclic Buffer. 27

MODE 0. 28

MODE 1. 29

MODE 2. 30

4.2 Quick Do Loop. 30

Full Software Solution. 30

Repeat Operation. 31

Macro. 32

Nesting. 32

4.3 Round off. 32

General idea about the Round off. 32

Instructions for Round off. 33

4.4 Long Word Multiplication. 33

4.5 Bit Stream Data Read/Write. 35

RAM Pointer bit assignment 36

Bit stream reading. 36

Bit stream writing. 37

4.6 Variable Length Code. 37

Huffman Decoder 37

4.7 Table Look Up. 40

4.8 Find Min/Max Value. 42

1. CD2470A Summary

This manual presents a comprehensive description of the Clarkspur’s 16 bit Fixed point DSP CD2470A Core. The 24 bit version (CD2480A) and the 32 bit version (CD2490A) of the DSP’s are also referred in this manual as the derivatives of the CD2470A. Actually, the CD2480A,90A have the same instruction set / architecture as that of CD2470A, except that the CD2480A,90A have different data register/memory bit width.

- Summary of the CD2470A -

· 16 bit Fixed point DSP with strong double word instructions.

· Compatible with standard single port clocked memory IP.

· Four sets of double word accumulator.

· Strong barrel shifter / normalizer.

· Bit stream data handling.

· Variable length code handling (e.g. Huffman code).

· Table look up capability.

· Instruction compatibility with higher precision DSP (CD2480A, CD2490A).

· No pipeline latency.

· 6% code space reserved for custom instructions.

· Verilog HDL Synthesizable design with visualized block diagrams.

· Communication port with outside Host hardware.

· 70MIPS for common 90nm Xilinx, Altera FPGA chips.

	CD2470A	CD2480A	CD2490A
Data bit width	16	24	32
Instruction bit width	16	16	16
Memory	Program 64Kx16 Data0 64Kx16 Data1 64Kx16	Program 16Mx16 Data0 16Mx24 Data1 16Mx24	Program 4Gx16 Data0 4Gx32 Data1 4Gx32

1.1 CD2470A Block Diagram

1.2 CD2470A Core Pin Summary

1.3 CD2470A Core – Memory Interface Diagram

1.4 CD2470A Basic Memory Access Timing Idea

1.5 CD2470A Register summary

1.6 CD2470A Registers Bit assignment

AL/AL0 (Accumulator-Low Register) Register Address=0

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0

A/AH/AH0 (Accumulator-High Register, Single word Accumulator) Register Address=1

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0

AL1/TL (Shadow Accumulator-Low Register) Register Address=2

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0

AH1/TH (Shadow Accumulator-High Register) Register Address=3

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0

AL2 (General Purpose-Low Register) Register Address=4

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0

AH2 (General Purpose -High Register) Register Address=5

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0

PL/AL3 (Product-Low Register) Register Address=6

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0

PH/AH3 (Product-High Register) Register Address=7

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0

X (MPYer input Register) Register Address=8

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0

Y (MPYer input Register) Register Address=9

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0

ST (Status Register) Register Address=10

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
N	OV	Z	CY	RZ	OP	IEx	IE2	IE1	IE0	PRL

PC (Program Counter) Register Address=11

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0

SP (Stack Pointer Register) Register Address=12

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
P15	P14	P13	P12	P11	P10	P9	P8	P7	P6	P5	P4	P3	P2	P1	P0

BF (PC I/F Buffer Register) Register Address=13 (SELBF=1)

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0

RC (Repeat Counter Register) Register Address=13 (SELBF=0)

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
n7	n6	n5	n4	n3	n2	n1	n0	m7	m6	m5	m4	m3	m2	m1	m0

TR (Temporary Register or Barrel Shifting bit counter Register [Lower 6 bit]) Register Address=14

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
T15	T14	T13	T12	T11	T10	T9	T8	T7	T6	T5	T4	T3	T2	T1	T0

PM (Temporary Register or Pointer Modifier Register [Lower 9 bit], Guard bit Register[15-9]) Register Address=15

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
M15	M14	M13	M12	M11	M10	M9	M8	M7	M6	M5	M4	M3	M2	M1	M0

1.7 CD2470A ALU Flag Updating Summary

Instructions	W	C	N	OV	Z	CY	RZ
ADSI Rij,#sSImm	1	1
Aop A,RAM,w	1	1
Aop Ad,As,(Rij),w	1	1
Aop Ad,As,Rij	1	1
Aop Ad,As,S,w	1	1
AopI Ad,As,#Imm	2	2
AopSI As,#Simm	1	1
BRA cond	2	2						* DRZi,NDRZi conditions only
CALL cond	2	2
INC (Rij) / DEC (Rij),cond	1	2
INC S / DEC S,cond	1	2
LD A,RAM,w / LD RAM,A,w	1	1
LD D,(Rij),w / LD (Rij),S,w	1	1
LD D,(Rij)p / LD (Rij)p,S	1	3/4