CD24x0A DSP S/W Development Tools

Debugger

The host interface port on the CD24x0A DSP cores allow easy core control with a small interface logic. An eight bit asynchronous parallel port for core control makes good communication with internal registers/memories from outside of the core. Utilizing this port, the CD24x0A Debugger S/W lets the core "RUN","STOP","SingleStep" and "READ/WRITE" data. A PC based HOST CPU may access to this port through USB I/F so that it visualizes the core contents on PC screen. You can "DOWNLOAD","UPLOAD" the program, data memories and registers from the tool. The Debugger has a "BREAK POINT" capability with which the program execution stops at program addresses where such break-points are set. Once the core stops its program execution with a break-point, you can execute a sequence of debugger commands. This feature enables "Virtual I/O" and other important functions needed for debugging target programs, and simulating the target hardware. Since FPGA vendors commonly offer good logic analyzer cells, most of hardware debugging involving target program have gotten incredibly easy. A pure S/W based simulator of the core is missing its meaning rapidly now, as long as a handy EVA boards and debugger exist.

Assembler

The CD24x0A series of DSP cores have a same instruction set, except that some of longer word versions have two word immediate data instructions besides the original CD24x0A instruction set. The CD24x0A debugger comes with an assembler sub window from which users can compose source program files, and assemble them.

VB6 based

All the CD24x0A related Tool S/Ws stand on the VB6 language. Any S/W modification necessary in modifying existing CD24x0A DSP core designs would be directly possible at customer's site by modifying the VB6 source code.

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