Bit Stream Read/Write
The CD24x0A can handle double word DRAM access, with that a seamless bit streaming RAM access is available through several special instructions. Assuming a bit stream data is stored in the sequence shown in the fig 1., the word pointer Wp and the bit position pointer Bp will point the current bit position in the whole bit stream stored in the RAM1,RAM0. There are two kinds of bit counting direction. One count the bit from MSB to LSB(m=0), the other LSB to MSB(m=1). Also, there are two cases when the target bit granule(n bit) resides across the word boundary. Here, we assume the target bit granule size is equal or less than the word size. We can use Rij pointers as the Wp word pointers, and the TR[4:0] register for Bp, hereafter.
Fig 1. Bit stream data storage and construction
RAM Pointer bit assignment
The RAM bit address pointer register is composed of one pair of [R4,R0],
[R5,R1], [R6,R2], [R7,R3], RAM pointers and LSB five bits of the TR register
as shown in Fig 2.
One pair of data words {(Ri+4),(Ri)} are accessed at a time, reading or
writing 32 bit long word, where the bit address on the long word is designated
by the TR[4:0]. Since the contents of (Ri+4) and (Ri) are modified independently,
arbitrary number (less or equal to 16) of bits from any bit-word address
is readable or writable as shown in Fig 1.
Bit stream reading
A bit string having a length "n" bit is read out from a buffer memory formed in the DRAM conveniently by utilizing LD and SHL instructions. It needs 3 or 4 cycles to read up to 16 bit bit-stream data from the memory composed in RAM1,0. A double word reading with or without word swapping is done with LD in double word mode and thereafter a couple of SHL instructions cut out the necessary part of the words as the final bit stream data onto one of Accumulators. Bit address pointers are updated with the MODB instruction for successive reading.
Fig. 3 Bit stream reading
Bit stream writing
Writing a bit string having a length "n" to the top of existing
bit stream in DRAM is conveniently programmed by utilizing SHL and LD
instructions. It needs 5 cycles to write up to 16 bit stream data to a
buffer memory area composed in RAM1,0. A double word reading with or without
word swapping is done with LD in double word mode and thereafter a couple
of SHL instructions cut out the necessary part of the words so that the
current bit stream data is patched with it. Finally the patched data is
written back into the DRAM. This routine takes either 5 or 6 cycles depending
on the bit streaming direction.
Fig. 4 Bit stream writing
