Memory and I/O Interface Clocked IP RAM, Asynchronous I/O The CD24x0A DSP cores may access up to three memory blocks. One program memory and two data memories. Any I/O port may be assigned on any memory address space if necessary. Many RAM IP available on silicon resource have a specification that needs a clock with synchronous address and control signals. The CD24x0A DSP cores are directly compatible with such memories.

Need Cache ?

Two types of clocked memories are very common as either IP cores or stand alone chips. Both types read address and control signals (RD, WR) at the beginning of a clock cycle, and output the read out data before the beginning of next clock cycle. Some of stand alone memory chips often make this reading out delay from the address input as a full clock cycle (meaning the data is available on or after the next clock cycle.) for faster clock frequency operation. Only the 'No latency' stand alone memories or common IP memories read back the data in the same clock cycle as shown in the figure. When seeing the write timing of these memories, most common IP memories have the timing of either Type1 or Type2 figured. If your target memory is something like Type1, then the CD24x0A DSP core can communicate with the memory in back-to-back. No additional interfacing logics are necessary. However, if the target memory timing is like Type2, where the writing data has to be available at the beginning of the cycle, you need to add small cache logic (one or more words) to convert the write timing from Type1 to Type2.

For the asynchronous I/O port, you can obtain necessary signals by latching the address and control signal at the beginning of the cycle before they are used. Control signals may need to be ANDed with inverse of Clock before using.

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