CD24x0A HDL Description HDL description The CD24x0A DSP cores go into any design form from the 'Detailed Block Diagram'. Most common representation of the design is the one with HDL(Hardware Description Language) . Clarkspur picked Verilog HDL that is one of the most popular HDLs on market. Either engineers or computerized tools can translate the Verilog HDL code to another HDL like VHDL easily. Once HDL is generated, a lot of backend design tools lead the design down to physical IC chips almost automatically.

One-to-one HDL description

Since Clarkspur's DSP core products come with all the background information of the designs, the HDL description is not the only resource that users can utilize for their core importing or modification work. In this viewpoint, we tried to make the HDL description as close as that of 'Detailed Block Diagram' using simple assign and always@ statements only, as long as its not too lengthy. Signal names, register names on the 'Detailed Block Diagram' appears on the HDL description so that users can trace the HDL interpretation without knowing whole DSP design.

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