CD2450 DSP Core Summary

Features

• 20 ns/cycle : adjustable bit length (16 - 24 bit) fixed point DSP.
• Acc + Ai * Bi --> Acc calculation in 20 ns.
• 16 x 16 bit --> 31 bit Two cycle pipelined/ Multiplier.
• 512 to 128K word (16 bit/word) Data RAM.
• Up to 64K word program/data memory space.
• Very simple uP type instruction set.
• Up to eight user definable registers.
• Adjustable data bit width keeping same instruction set from 16 to 24 bit.
• 160 pin QFP (1Kw x 2 on chip DRAM, off chip PRAM) EVA-Chip. --- Hand Drawn Version.
• 208 pin QFP (4Kw+6Kw on chip DRAM, 16Kw on chip PRAM) EVA-Chip --- HDL synthesized Version.
• Available as a CORE cell (70 x 18 mil2 in 0.35 u :excl. RAM) for highly integrated custom design.
• Available in transistor level full custom layout cell.
• VHDL model (Synthesizable), Verilog model (Synthesizable) are available with efficient script file.
• Emulator, Simulator/Debugger, Assembler/Dis-assembler, MATLAB I/F available.

More description for the CD2450

Block Diagram

CD2450 Instruction Summary

Mnemonic             W C  Operation

LD D,S               1 1 D reg. <- S reg.
LD D,(Ri)            1 1 D reg. <- Data RAM (Ri)
LD (Ri),S            1 1 Data RAM (Ri) <- Sreg.
LD A,add             1 1 AH <- Data RAM (add:9bit)
LD add,A             1 1 Data RAM (add:9bit) <- AH 
LD D,(Ri)p           1 3 D reg. <- Program Mem (Ri)
LD (Ri)p,S           1 4 Program Mem (Ri) <- S reg.
LD D,(S)p            1 3 D reg. <- Program Mem (S reg)
LDI D,Imm            2 2 D reg. <- Immediate Data (16bit)
LDI Ri,Imm           2 2 Ri Pointer <- Immediate Data (16bit)
LDI (Ri),Imm         2 2 Data RAM (Ri) <- Immediate Data (16bit)
LD D,Ri              1 1 D reg. <- Ri Pointer
LD Ri,S              1 1 Ri Pointer <- S reg.
LDSI Ri,SImm         1 1 Ri Pointer <- Short Immediate Data (10bit)
LDSI A,SImm          1 1 AH <- Short Immediate Data (10bit)
ADD A,S,h,c          1 1 AH <- AH + S reg. + 
ADD A,(Ri),h,c       1 1 AH <- AH + Data Ram (Ri)  + 
ADD A,add            1 1 AH <- AH + Data Ram (add)  + 
ADD A,(Ri)p,h,c      1 3 AH <- AH + Program Mem (Ri)  + 
ADDI A,Imm,c         2 2 AH <- AH + Immediate Data (16bit) + 
ADD A,Ri,h,c         1 1 AH <- AH + Ri pointer  + 
ADSI A,SImm          1 1 AH <- AH + Short Immediate Data (10bit:Unsigned)
SUB A,S,h,c          1 1 AH <- AH - S reg. + 
SUB A,(Ri),h,c       1 1 AH <- AH - Data Ram (Ri)  + 
SUB A,add            1 1 AH <- AH - Data Ram (add)  + 
SUB A,(Ri)p,h,c      1 3 AH <- AH - Program Mem (Ri)  + 
SUBI A,Imm,c         2 2 AH <- AH - Immediate Data (16bit) + 
SUB A,Ri,h,c         1 1 AH <- AH - Ri pointer  + 
SUSI A,SImm          1 1 AH <- AH - Short Immediate Data (10bit:Unsigned)
CMP A,S,h,c          1 1 AH - S reg. + 
CMP A,(Ri),h,c       1 1 AH - Data Ram (Ri)  + 
CMP A,add            1 1 AH - Data Ram (add)  + 
CMP A,(Ri)p,h,c      1 3 AH - Program Mem (Ri)  + 
CMPI A,Imm,c         2 2 AH - Immediate Data (16bit) + 
CMP A,Ri,h,c         1 1 AH - Ri pointer  + 
CPSI A,SImm          1 1 AH - Short Immediate Data (10bit:Unsigned)
AND A,S              1 1 AH <- AH and S reg.
AND A,(Ri)           1 1 AH <- AH and Data Ram (Ri)
AND A,add            1 1 AH <- AH and Data Ram (Ri)
AND A,(Ri)p          1 3 AH <- AH and Program Mem (Ri)
ANDI A,Imm           2 2 AH <- AH and Immediate Data (16bit)
AND A,Ri             1 1 AH <- AH and Ri Pointer
ANSI A,SImm          1 1 AH <- AH and Short Immediate Data (10bit)
OR A,S               1 1 AH <- AH or S reg.
OR A,(Ri)            1 1 AH <- AH or Data Ram (Ri)
OR A,add             1 1 AH <- AH or Data Ram (Ri)
OR A,(Ri)p           1 3 AH <- AH or Program Mem (Ri)
ORI A,Imm            2 2 AH <- AH or Immediate Data (16bit)
OR A,Ri              1 1 AH <- AH or Ri Pointer
ORSI A,SImm          1 1 AH <- AH or Short Immediate Data (10bit)
EOR A,S              1 1 AH <- AH eor S reg.
EOR A,(Ri)           1 1 AH <- AH eor Data Ram (Ri)
EOR A,add            1 1 AH <- AH eor Data Ram (Ri)
EOR A,(Ri)p          1 3 AH <- AH eor Program Mem (Ri)
EORI A,Imm           2 2 AH <- AH eor Immediate Data (16bit)
EOR A,Ri             1 1 AH <- AH eor Ri Pointer
EOSI A,SImm          1 1 AH <- AH eor Short Immediate Data (10bit)
BRA add,cond         2 2 Branch to add.(16bit) if the condition is met.
CALL add,cond,B      2 2 Subroutine Call if the condition is met.
RET B                1 3 Return from a subroutine.
MLD (Rj),(Rk),b      1 1 X <- (Rk), Y <- (Rj), AH|AL <- 0
MSET (Rj),(Rk),b     1 1 X <- (Rk), Y <- (Rj)
MPYA (Rj),(Rk),b     1 1 X <- (Rk), Y <- (Rj), AH|AL <- AH|AL + PH|PL
MPYS (Rj),(Rk),b     1 1 X <- (Rk), Y <- (Rj), AH|AL <- AH|AL - PH|PL
MLD S,(Rk),b         1 1 X <- (Rk), Y <- S reg., AH|AL <- 0
MSET S,(Rk),b        1 1 X <- (Rk), Y <- S reg.
MPYA S,(Rk),b        1 1 X <- (Rk), Y <- S reg., AH|AL <- AH|AL + PH|PL
MPYS S,(Rk),b        1 1 X <- (Rk), Y <- S reg., AH|AL <- AH|AL - PH|PL
DADD h               1 1 AH|AL <- AH|AL + PH|PL 
DSUB h               1 1 AH|AL <- AH|AL - PH|PL 
TST S,bit            1 2 Test the bit of S reg.
SET S,bit            1 2 Set the bit of S reg.
RES S,bit            1 2 Reset the bit of S reg.
TGL S,bit            1 2 Toggle the bit of S reg.
TST (Ri),bit         1 2 Test the bit of Ram Data (Ri).
SET (Ri),bit         1 2 Set the bit of Ram Data (Ri).
RES (Ri),bit         1 2 Reset the bit of Ram Data (Ri).
TGL (Ri),bit         1 2 Toggle the bit of Ram Data (Ri).
INC S,cond           1 2 S reg. <- S reg. + 1 if the condition is met.
INC (Ri),cond        1 2 Data Ram (Ri) <- Data Ram (Ri) + 1 if cond. is met.	
DEC S,cond           1 2 S reg. <- S reg. - 1 if the condition is met,
DEC (Ri),cond        1 2 Data Ram (Ri) <- Data Ram (Ri) - 1 if cond. is met.
MODR Rj,Rk           1 1 Modify Pointers.
MOD op,cond,m        1 1 AH or AH|AL modification. Shift,Swap,Negate,Abs,Cpl.
MODF op,slp          1 1 Flag Set/Reset. CY,OP,IE,SLEEP.
NOP                  1 1 No operation.


##  W: Number of instruction words.
           1... one word instruction.      2... two word instruction.
##  C: Execution  Cycles.  ( +1 depending on the condition)