Evaluation Board FPGA based Evaluation chip Once an application chip is composed based on the CD24x0A DSP core in HDL, the hardware of the application chip may be just a snap away. The FPGA hardware capacity is now overwhelming a small logic like CD24x0A cores. Even a free version of the FPGA S/W Tools are enough for CD24x0A chip evaluation hardware size. Clarkspur provides an evaluation board that can run at 20MIPS with Xilinx FPGA chip. A 50MIPS version is also available at request.

Standard Stereo Analog Codec I/F, Flash Memory

The CD24x0A evaluation board comes in very limited memory size due that only FPGA on-chip RAMs are used for implementation . Current EVA board utilizes Xilinx XC2V1000 chip with PCM3006 Stereo codec and 8Mbit Data Flash memory in 4" x 2.5" x 1" plastic case. It comes with USB1.1 for host PC interface, as well. The board is self powered by USB port. Driver S/W for Windows98, ME, 2000, NT, XP and associated board control S/W are available.

Clarkspur also provides little faster version (50MIPS) on the EVA board utilizing Xilinx latest version FPGA Virtex4, with large outside memory at customer's request. A little further more fast version is available using Altera StaratixII FPGA if necessary.

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