CD24x0A Control Logic Design Control Logic Diagram By controlling around one hundred gate signals depending on instructions and machine state, the CD24x0A DSPs continue to execute program. Such combinational logic with instruction and machine state as input , and all the gate control signals as output is one of the most annoying parts in the DSP design. While CD24x0A DSPs employ shortest (no) pipeline architecture, there are no specific time slots for instruction decoding. Very careful code assignment is necessary to minimize the logic for fast instruction decoding.

Control Signal Design

Each gate control signal has one page of 'Control Signal Diagram' like the figure in CD24x0A DSP design resource, as long as it wouldn't be too much redundant. All the instructions are mapped on the diagram, where only necessary conditions for the output signal are marked in a color. If such colored parts are scattered randomly on a diagram, the decoding logic for the control signal will be big and slow. We may need to rearrange the code assignment to minimize the logic, if there is any critical path on it. Some signal may be slow, some are fast with delayed 'machine state' input involved. Although just one sheet of such diagram cannot tell all the condition and requirement for the gate control signal, it would help the control signal design work, and the later modification as well.

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