CD24x0A DSP Detailed Block Diagram All the gates are described on the diagram. Once the basic architecture is determined, more detailed block diagram describing all the BUS, Register and Gates will be made. Each gate has a specific gate control signal name. Although the gate symbol does not necessarily mean simple input gate, this diagram determines the data path logic details so that actual HDL coding is uniquely possible with it. Every instruction gives a sequence of gating signal to each gate so that it completes an instruction in less than a few cycles. Most of the instructions take only one clock cycle to complete.

CD24x0A Detailed Block Diagram

An overall core block diagram is presented first, then the core is decomposed into several functional blocks. Each functional block can be coded either in Verilog HDL, VHDL or even Schematic diagram. Current Clarkspur IPs are using Verilog HDL due to its popularity in market. However, the design is absolutely common down to this 'Detailed Block Diagram' level, whether you pick HDL or Schematic thereafter.

Overall Block Diagram



Detailed Functional Block Diagram

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