CD24x0A DSP Block Diagram

DSP Design Starts here.

A rough diagram of bus structure would make the DSP design easier. It is useful for visualizing the effectiveness of each BUS, checking the feasibility of special instruction, balancing the time delay of each element, estimating the logic size, figuring out the final silicon layout.... Before getting into a detail, we have a lot to do with this simple diagram.

Simple and Widely accepted Architecture

All of Clarkspur DSP cores employ one simple architecture with Multiply-Add in one cycle latency as in this block diagram. A multiplier reads two memory data to generate a 'product' in a cycle, then the product goes to one of two inputs of the ALU followed. This Multiply-Add is done in one clock cycle. Thanks to this simple timing structure, the DSPs do not ask programmers to insert any NOPs to wait for data availability as frequently seen in highly pipelined DSPs. Having no latency architecture sometimes limits the DSP performance at very special case where highly pipelined architecture may be effective. However, there are more applications that may need only simple Multiply-Add in no latency. Today's common DSPs are expanding its capacity in both data pipelining (Time ) and very long instruction word (Program Memory Size). However, there are far more applications needing a little lower MIPS but smaller size and easy adoption to other design elements. Seeing high performance signal processing chips are now replaced with more hardware oriented solution rather than sticking with a 'Highly pipelined CPU-DSP' solution whereas low-end applications still need CPU-DSP for best cost-performance, Clarkspur is been carefully choosing the architecture size for its new CPU-DSP core products depending on current 'process' cost/availability.

CD2470A Block Diagram

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